Aula5

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Aula 5: Pipelining (parte 2 – Caminho de Dados)
Professor: Leandro Marzulo
Arquiteturas Avançadas de Computadores
Pipeline Clássico do MIPS
5 etapas:
Buscar instrução na memória.
Ler registradores enquanto a instrução é decodificada.
Executar a operação ou calcular um endereço.
Acessar a memória de dados.
Escrever o resultado em um registrador
2
Dividindo o projeto Monociclo
3
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF
ID
EX
MEM
WB
Dividindo o projeto Monociclo
4
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF
ID
EX
MEM
WB
HAZARDS!
Dividindo o projeto Monociclo
5
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Onde está o bug?
LW - IF
6
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
LW - ID
7
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
LW - EX
8
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
LW - MEM
9
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
Address
Read Data
Data Memory
Write Data
LW - WB
10
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
LW – Unidades Usadas
11
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
PC
4
Instruction [15-11]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
Address
Read Data
Data Memory
Write Data
Solução do bug
12
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Instruction [20-16]
0
1
Sign
Extend
Instruction [15-0]
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Instruction [20-11]
64 bits
138 bits
102 bits
69 bits
Tamanho dos registradores de pipe?
Instruction [15-11]
Representação gráfica
Como se cada instrução tivesse seu caminho de dados (mas não é verdade)
IM
REG
ALU
DM
REG
lw $t0, 10($t1)
sw $t3, 20($t4)
add $t5, $t6, $t7
CC 1
CC 2
CC 3
CC 4
CC 5
CC 6
CC 7
IM
REG
ALU
DM
REG
IM
REG
ALU
DM
REG
sub
 $t8, $t9, $s5
IM
REG
ALU
DM
REG
CC 8
Time axis
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
lw $t0, 10($t1)
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
sw $t3, 20($t4)
lw $t0, 10($t1)
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
add $t5, $t6, $t7
lw $t0, 10($t1)
sw $t3, 20($t4)
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
add $t5, $t6, $t7
lw $t0, 10($t1)
sw $t3, 20($t4)
sub $t8, $t9, $s5
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
add $t5, $t6, $t7
lw $t0, 10($t1)
sw $t3, 20($t4)
sub $t8, $t9, $s5
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
add $t5, $t6, $t7
LW acabou!
sw $t3, 20($t4)
sub $t8, $t9, $s5
Instruction [15-0]
SW passa por WB sem usar nada
Add passa por MEM sem usar nada
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
add $t5, $t6, $t7
sub $t8, $t9, $s5
Instruction [15-0]
SW terminou
Sub passa por MEM sem fazer nada
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Add terminou!
sub $t8, $t9, $s5
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Como é na realidade
 Add
Zero
 
Result
.
Read address
Instruction
[31 – 0]
Instruction Memory
Address
Read Data
Data Memory
Write Data
Read Register 1
Read Data 1
Read Register 2
Read Data 2
Write Register
Register File
Write Data
PC
4
Instruction [20-16]
Sign
Extend
Instruction [25-21]
16
0
1
32
1
0
<<2
 Add
0
1
IF/ID
ID/EX
EX/MEM
MEM/WB
Sub terminou!
Instruction [15-0]
Instruction [20-16]
0
1
Instruction [20-11]
Instruction [15-11]
Contatos
23
leandro@ime.uerj.br
lmarzulo@cos.ufrj.br
leandro.marzulo@gmail.com