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ALU_16bits.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ALU_16bits is
port (EntA,EntB:in std_logic_vector (15 downto 0);
EntF: in std_logic_vector (1 downto 0);
saiS:out std_logic_vector (15 downto 0);
SaiN,SaiZ: out std_logic);
end ALU_16bits;
architecture estrutural of ALU_16bits is
component ALU_Algoritmica_1bit
port (EntA,EntB:in std_logic;
Cin: in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS:out std_logic;
Cout: out std_logic);
end component;
signal S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16: std_logic;
signal Cout1,Cout2,Cout3,Cout4,Cout5,Cout6,Cout7,Cout8,Cout9,Cout10,Cout11,Cout12,Cout13,Cout14,Cout15,Cout16: std_logic;
begin
M00:ALU_Algoritmica_1bit port map (EntA(0),EntB(0),'0',EntF,S1,Cout1);
M01:ALU_Algoritmica_1bit port map (EntA(1),EntB(1),Cout1,EntF,S2,Cout2);
M02:ALU_Algoritmica_1bit port map (EntA(2),EntB(2),Cout2,EntF,S3,Cout3);
M03:ALU_Algoritmica_1bit port map (EntA(3),EntB(3),Cout3,EntF,S4,Cout4);
M04:ALU_Algoritmica_1bit port map (EntA(4),EntB(4),Cout4,EntF,S5,Cout5);
M05:ALU_Algoritmica_1bit port map (EntA(5),EntB(5),Cout5,EntF,S6,Cout6);
M06:ALU_Algoritmica_1bit port map (EntA(6),EntB(6),Cout6,EntF,S7,Cout7);
M07:ALU_Algoritmica_1bit port map (EntA(7),EntB(7),Cout7,EntF,S8,Cout8);
M08:ALU_Algoritmica_1bit port map (EntA(8),EntB(8),Cout8,EntF,S9,Cout9);
M09:ALU_Algoritmica_1bit port map (EntA(9),EntB(9),Cout9,EntF,S10,Cout10);
M10:ALU_Algoritmica_1bit port map (EntA(10),EntB(10),Cout10,EntF,S11,Cout11);
M11:ALU_Algoritmica_1bit port map (EntA(11),EntB(11),Cout11,EntF,S12,Cout12);
M12:ALU_Algoritmica_1bit port map (EntA(12),EntB(12),Cout12,EntF,S13,Cout13);
M13:ALU_Algoritmica_1bit port map (EntA(13),EntB(13),Cout13,EntF,S14,Cout14);
M14:ALU_Algoritmica_1bit port map (EntA(14),EntB(14),Cout14,EntF,S15,Cout15);
M15:ALU_Algoritmica_1bit port map (EntA(15),EntB(15),Cout15,EntF,S16,Cout16);
saiS(0) <= S1;
saiS(1) <= S2;
saiS(2) <= S3;
saiS(3) <= S4;
saiS(4) <= S5;
saiS(5) <= S6;
saiS(6) <= S7;
saiS(7) <= S8;
saiS(8) <= S9;
saiS(9) <= S10;
saiS(10) <= S11;
saiS(11) <= S12;
saiS(12) <= S13;
saiS(13) <= S14;
saiS(14) <= S15;
saiS(15) <= S16;
saiN <= S16;
saiZ <= (not(((((((((((((((S16 or S15) or S14) or S13) or S12) or S11) or S10) or S9) or S8) or S7) or S6) or S5) or S4) or S3) or S2) or S1));
end estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchALU_16 is
end testbenchALU_16;
architecture teste of testbenchALU_16 is
component ALU_16bits
port (EntA,EntB:in std_logic_vector (15 downto 0);
EntF: in std_logic_vector (1 downto 0);
saiS:out std_logic_vector (15 downto 0);
SaiN,SaiZ: out std_logic);
end component;
signal sigA,sigB,sigS:std_logic_vector (15 downto 0);
signal sigF:std_logic_vector (1 downto 0);
signal sigN,sigZ:std_logic;
begin
comp:ALU_16bits port map (sigA,sigB, sigF,sigS, sigN, sigZ);
process
begin
sigA<="0000000000000000","0000000000000001" after 2 ns;
sigB<="0000000000000001","0000000000000011" after 4 ns;
sigF<="00","01" after 6 ns,"11" after 8 ns, "10" after 10 ns;
wait;
end process;
end teste;
ALU_algoritmica_1bit.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ALU_Algoritmica_1bit is
port(EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end ALU_Algoritmica_1bit;
architecture ALU_Algo_1bit of ALU_Algoritmica_1bit is
begin
process (EntA, EntB, Cin, EntF)
begin
--Caso seja a opcao 00 = A+B
if EntF(1)='0' and EntF(0)='0' then
if Cin = '0' then
if EntA = '0' then
if EntB = '0' then
SaiS <= '0';
Cout <= '0';
else
SaiS <= '1';
Cout <= '0';
end if;
else
if EntB = '0' then
SaiS <= '1';
Cout <= '0';
else
SaiS <= '0';
Cout <= '1';
end if;
end if;
else
if EntA = '0' then
if EntB = '0' then
SaiS <= '1';
Cout <= '0';
else
SaiS <= '0';
Cout <= '1';
end if;
else
if EntB = '0' then
SaiS <= '0';
Cout <= '1';
else
SaiS <= '1';
Cout <= '1';
end if;
end if;
end if;
--Caso seja a opcao 01 = AB
elsif EntF(1) = '0' and EntF(0) = '1' then
if EntA='1' and EntB='1' then
SaiS <= '1';
else
SaiS <= '0';
end if;
--Caso seja a opcao 10 = A
elsif EntF(1) = '1' and EntF(0) = '0' then
if EntA = '1' then
SaiS <= '1';
else
SaiS <= '0';
end if;
--Caso seja a opcao 11 = NOT(A)
else
if EntA = '0' then
SaiS <= '1';
else
SaiS <= '0';
end if;
end if;
end process;
end ALU_Algo_1bit;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchALU_1bit_algoritimica is
end testbenchALU_1bit_algoritimica;
architecture teste of testbenchALU_1bit_algoritimica is
component ALU_Algoritmica_1bit
port (EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end component;
signal sigA,sigB,sigCin,sigS, sigCout: std_logic;
signal sigF: std_logic_vector(1 downto 0);
begin
comp: ALU_Algoritmica_1bit port map (sigA,sigB, sigCin, sigF, sigS, sigCout);
process
begin
sigA<='0','1' after 2 ns,'0' after 12 ns, '1' after 14 ns;
sigB<='0','1' after 4 ns, '0' after 12 ns, '1' after 16 ns;
sigCin<='0','1' after 12 ns;
sigF<="00","01" after 6 ns,"11" after 8 ns, "10" after 10 ns, "00" after 14 ns,
"01" after 20 ns, "11" after 22 ns,"10" after 24 ns;
wait;
end process;
end teste;
ALU_estrutural_1bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ALU_estrutural_1bit is
port(EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end ALU_estrutural_1bit ;
architecture estrutural of ALU_estrutural_1bit is
component AND2
port (E1,E2:in std_logic; S: out std_logic);
end component;
component INV
port (E: in std_logic; S: out std_logic);
end component;
--component XOR2
-- port (E1,E2:in std_logic; S: out std_logic);
--end component;
component OR2
port (E1,E2:in std_logic; S: out std_logic);
end component;
signal S1,S2,S3,S4,S5,S6,S7,S8,S9,S10: std_logic;
signal S11,S12,S13,S14,S15,S16,S17,S18,S19,S20: std_logic;
begin
-- calculo dos inversos das entradas de controle - NOT(F0),NOT(F1)
P1: INV port map (EntF(1),S1);
P2: INV port map (EntF(0),S2);
-- combinacoes dos controle - F0,F1,NOT(F0),NOT(F1)
P3: AND2 port map (S1,S2,S3);
P4: AND2 port map (S1,EntF(0),S4);
P5: AND2 port map (EntF(1),S2,S5);
P6: AND2 port map (EntF(1),EntF(0),S6);
--COMBINACAO DAS ENTRADAS - A+B, AB, NOT(A)
P7: OR2 port map (EntA,EntB,S7);
P8: AND2 port map (EntA,EntB,S8);
P9: INV port map (EntA,S9);
--COMBINACAO DA ENTRADA A+B + Cin
P10: AND2 port map (S7,Cin,S10);
--Combinacao entre os controle e entradas
P11: AND2 port map (S3,S10,S11);
P12: AND2 port map (S4,S8,S12);
P13: AND2 port map (S5,S9,S13);
P14: AND2 port map (S6,EntA,S14);
--COMBINACAO DE TODOS OS RESULTADOS
P15: OR2 port map (S11,S12,S15);
P16: OR2 port map (S15,S13,S16);
P17: OR2 port map (S16,S14,SaiS);
--PARA CALCULO DO cOUT
P18: OR2 port map (S10,S8,Cout);
END estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchALU_estrutural_1bit is
end testBenchALU_estrutural_1bit;
architecture teste_estrutural of testBenchALU_estrutural_1bit is
component ALU_estrutural_1bit
port (EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end component;
signal sigA,sigB,sigCin,sigS, sigCout: std_logic;
signal sigF: std_logic_vector(1 downto 0);
begin
comp: ALU_estrutural_1bit port map (sigA,sigB, sigCin, sigF, sigS, sigCout);
process
begin
sigA<='0','1' after 2 ns,'0' after 12 ns, '1' after 14 ns;
sigB<='0','1' after 4 ns, '0' after 12 ns, '1' after 16 ns;
sigCin<='0','1' after 12 ns;
sigF<="00","01" after 6 ns,"11" after 8 ns, "10" after 10 ns, "00" after 14 ns,
"01" after 20 ns, "11" after 22 ns,"10" after 24 ns;
wait;
end process;
end teste_estrutural;
ALU_fluxo_1bit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ALU_fluxo_1bit is
port(EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end ALU_fluxo_1bit;
architecture fluxo of ALU_fluxo_1bit is
begin
saiS<= ((not(EntF(1)) and not(EntF(0)) and((EntA xor EntB) xor Cin)) or
(not(EntF(1)) and EntF(0)and EntA and EntB) or
(EntF(1) and not(EntF(0)) and EntA) or
(EntF(1) and EntF(0) and not(EntA)));
Cout<= (not(EntF(0)) and not(EntF(1)) and ((EntA and EntB) xor (Cin and (EntA xor EntB))));
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchALU_fluxo_1bit is
end testbenchALU_fluxo_1bit;
architecture teste of testbenchALU_fluxo_1bit is
component ALU_fluxo_1bit
port (EntA,EntB,Cin:in std_logic;
EntF: in std_logic_vector (1 downto 0);
SaiS: out std_logic;
Cout: out std_logic);
end component;
signal sigA,sigB,sigCin,sigS,sigCout: std_logic;
signal sigF: std_logic_vector(1 downto 0);
begin
comp: ALU_fluxo_1bit port map (sigA,sigB, sigCin, sigF, sigS, sigCout);
process
begin
sigA<='0','1' after 2 ns,'0' after 12 ns, '1' after 14 ns;
sigB<='0','1' after 4 ns, '0' after 12 ns, '1' after 16 ns;
sigCin<='0','1' after 12 ns;
sigF<="00","01" after 6 ns,"11" after 8 ns, "10" after 10 ns, "00" after 14 ns,
"01" after 20 ns, "11" after 22 ns,"10" after 24 ns;
wait;
end process;
end teste;
Componentes.vhd
library ieee;
use ieee.std_logic_1164.all;
entity AND2 is
port (E1,E2: in std_logic; S: out std_logic);
end AND2;
architecture fluxo of AND2 is
begin
S <= E1 AND E2;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity INV is
port (E:in std_logic; S: out std_logic);
end INV;
architecture fluxo of INV is
begin
S <= not (E);
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity OR2 is
port (E1,E2: in std_logic; S: out std_logic);
end OR2;
architecture fluxo of OR2 is
begin
S <= E1 OR E2;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity AND5 is
port (E1,E2,E3,E4,E5: in std_logic; S: out std_logic);
end AND5;
architecture fluxo of AND5 is
begin
S <= E1 AND E2 AND E3 AND E4 and E5;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity OR3 is
port (E1,E2,E3: in std_logic; S: out std_logic);
end OR3;
architecture fluxo of OR3 is
begin
S <= E1 OR E2 or E3;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity AND3 is
port (E1,E2,E3: in std_logic; S: out std_logic);
end AND3;
architecture fluxo of AND3 is
begin
S <= E1 AND E2 AND E3;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity OR4 is
port (E1,E2,E3,E4: in std_logic; S: out std_logic);
end OR4;
architecture fluxo of OR4 is
begin
S <= E1 OR E2 or E3 or E4;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity XOR2 is
port (E1,E2: in std_logic; S: out std_logic);
end XOR2;
architecture fluxo of XOR2 is
begin
S <= E1 XOR E2;
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity NOR2 is
port (E1,E2: in std_logic; S: out std_logic);
end NOR2;
architecture fluxo of NOR2 is
begin
S <= E1 NOR E2;
end fluxo;
Controlador.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity controlador_cpu is
port(n,z,clk: in std_logic;
amux,mbr,mar,rd,wr,enc: out std_logic;
ula,sh:out std_logic_vector(1 downto 0);
a,b,c:out std_logic_vector(3 downto 0)
);
end controlador_cpu;
architecture comportamental of controlador_cpu is
signal cond:std_logic_vector(1 downto 0);
signal estado_atual,addr:unsigned(7 downto 0);
begin
combinacao_de_estados: process (estado_atual)
begin
case estado_atual is
--mar:=pc; rd;
when "00000000" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--pc:=pc+1; rd;
when "00000001" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='1';c<="0000";b<="0110";a<="0000";
addr <= "00000000";
--ir:=mbr; if n then goto 28;
when "00000010" => amux<='1'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0011";b<="0000";a<="0000";
addr <= "00011100";
--tir:=lshift(ir+ir); if n then goto 19;
when "00000011" => amux<='0'; cond<="01"; ula<="00";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0011";a<="0011";
addr <= "00010011";
--tir:=lshift(tir); if n then goto 11;
when "00000100" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00001011";
--alu:=tir; if n then goto 9;
when "00000101" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00001001";
--mar:=ir; rd;
when "00000110" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='1';c<="0000";b<="0011";a<="0000";
addr <= "00000000";
--rd;
when "00000111" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--ac := mbr; goto 0;
when "00001000" => amux<='1'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0000";a<="0000";
addr <= "00000000";
--mar := ir; mbr := ac; wr;
when "00001001" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='1';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="0011";a<="0001";
addr <= "00000000";
--wr; goto 0;
when "00001010" => amux<='0'; cond<="11"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='1';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--alu := tir; if n then goto 15;
when "00001011" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00001111";
--mar:=ir; rd;
when "00001100" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='0';c<="0000";b<="0011";a<="0000";
addr <= "00000000";
--rd;
when "00001101" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--ac := mbr + ac; goto 0;
when "00001110" => amux<='1'; cond<="11"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0001";a<="0000";
addr <= "00000000";
--mar := ir; rd;
when "00001111" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='1';c<="0000";b<="0011";a<="0000";
addr <= "00000000";
--ac := ac + 1; rd;
when "00010000" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='1';c<="0001";b<="0001";a<="0110";
addr <= "00000000";
--a := inv (mbr);
when "00010001" => amux<='1'; cond<="00"; ula<="11";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0000";a<="0000";
addr <= "00000000";
--ac := ac + a; goto 0;
when "00010010" => amux<='0'; cond<="11"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='1';c<="0001";b<="0001";a<="1010";
addr <= "00000000";
--tir:=lshift(tir); if n then goto 25;
when "00010011" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00011001";
--alu := tir; if n then goto 23;
when "00010100" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00010111";
--alu := ac; if n then goto 0;
when "00010101" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0001";
addr <= "00000000";
--pc := band(ir, amask); goto 0;
when "00010110" => amux<='0'; cond<="11"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0000";b<="0011";a<="1000";
addr <= "00000000";
--alu := ac; if z then goto 22;
when "00010111" => amux<='0'; cond<="10"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0001";
addr <= "00010110";
--goto 0;
when "00011000" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--alu := tir; if n then goto 27;
when "00011001" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00011011";
--pc := band (ir, amask); goto 0;
when "00011010" => amux<='0'; cond<="11"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0000";b<="0011";a<="1000";
addr <= "00000000";
--ac := band (ir, amask); goto 0;
when "00011011" => amux<='0'; cond<="11"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0011";a<="1000";
addr <= "00000000";
--tir := lshift (ir + ir); if n then goto 40;
when "00011100" => amux<='0'; cond<="01"; ula<="00";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0011";a<="0011";
addr <= "00101000";
--tir := lshift (tir); if n then goto 35;
when "00011101" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00100011";
--alu := tir; if n then goto 33;
when "00011110" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00100001";
--a := ir + sp;
when "00011111" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00000111";
--mar := a; rd; goto 7;
when "00100000" => amux<='1'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0011";b<="0000";a<="0000";
addr <= "00000111";
--a := ir + sp;
when "00100001" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00000000";
--mar := a; mbr := ac; wr; goto 10;
when "00100010" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='1';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="1010";a<="0001";
addr <= "00001010";
--alu := tir; if n then goto 38;
when "00100011" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00100110";
--a := ir + sp;
when "00100100" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00000000";
--mar := a; rd; goto 13;
when "00100101" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00001101";
--a := ir + sp;
when "00100110" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00000000";
--mar := a; rd; goto 16;
when "00100111" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0010";a<="0011";
addr <= "00001101";
--tir := lshift (tir); if n then goto 46;
when "00101000" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00101110";
--alu := tir; if n then goto 44;
when "00101001" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00101100";
--alu := ac; if n then goto 22;
when "00101010" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0001";
addr <= "00010110";
--goto 0;
when "00101011" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--alu := ac; if z then goto 0;
when "00101100" => amux<='0'; cond<="10"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0001";
addr <= "00000000";
--pc := band (ir, amask); goto 0;
when "00101101" => amux<='0'; cond<="11"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0000";b<="0011";a<="1000";
addr <= "00000000";
--tir := lshift (tir); if n then goto 50;
when "00101110" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00110010";
--sp := sp + (-1);
when "00101111" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0010";b<="0111";a<="0010";
addr <= "00000000";
--mar := sp; mbr := pc; wr;
when "00110000" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='1';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="0010";a<="0000";
addr <= "00000000";
--pc := band (ir + amask); wr; goto 0;
when "00110001" => amux<='0'; cond<="11"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='1';enc<='1';c<="0000";b<="0011";a<="1000";
addr <= "00000000";
--tir := lshift (tir); if n then goto 65;
when "00110010" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "01000001";
--tir := lshift (tir); if n then goto 59;
when "00110011" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "00111011";
--alu := tir; if n then goto 56;
when "00110100" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00111000";
--mar := ac; rd;
when "00110101" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='0';c<="0000";b<="0001";a<="0000";
addr <= "00000000";
--sp := sp + (-1); rd;
when "00110110" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='1';c<="0010";b<="0111";a<="0010";
addr <= "00000000";
--mar := sp; wr; goto 10";
when "00110111" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="0010";a<="0000";
addr <= "00001010";
--mar := sp; sp := sp + 1; rd;
when "00111000" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='1';c<="0010";b<="0110";a<="0010";
addr <= "00000000";
--rd;
when "00111001" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--mar := ac; wr; goto 10";
when "00111010" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="0001";a<="0000";
addr <= "00001010";
--alu := tir; if n then goto 62;
when "00111011" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "00111110";
--sp := sp + (-1);
when "00111100" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0010";b<="0111";a<="0010";
addr <= "00000000";
--mar := sp; mbr := ac; wr; goto 10";
when "00111101" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='1';
mar<='1';rd<='0';wr<='1';enc<='0';c<="0000";b<="0010";a<="0001";
addr <= "00001010";
--mar := sp; sp := sp + 1; rd;
when "00111110" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='1';c<="0010";b<="0110";a<="0010";
addr <= "00000000";
--rd;
when "00111111" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--ac := mbr; goto 0;
when "01000000" => amux<='1'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0000";a<="0000";
addr <= "00000000";
--tir := lshift (tir); if n then goto 73;
when "01000001" => amux<='0'; cond<="01"; ula<="10";sh<="01";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0100";b<="0000";a<="0100";
addr <= "01001001";
--alu := tir; if n then goto 70;
when "01000010" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "01000110";
--mar := sp; sp := sp + 1; rd;
when "01000011" => amux<='0'; cond<="00"; ula<="00";sh<="00";mbr<='0';
mar<='1';rd<='1';wr<='0';enc<='1';c<="0010";b<="0110";a<="0010";
addr <= "00000000";
--rd;
when "01000100" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='1';wr<='0';enc<='0';c<="0000";b<="0000";a<="0000";
addr <= "00000000";
--pc := mbr; goto 0;
when "01000101" => amux<='1'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0000";a<="0000";
addr <= "00000000";
--a := ac;
when "01000110" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="0000";a<="0001";
addr <= "00000000";
--ac := sp;
when "01000111" => amux<='0'; cond<="00"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0001";b<="0000";a<="0010";
addr <= "00000000";
--sp := a; goto 0;
when "01001000" => amux<='0'; cond<="11"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0010";b<="0000";a<="1010";
addr <= "00000000";
--alu := tir; if n then goto 76;
when "01001001" => amux<='0'; cond<="01"; ula<="10";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='0';c<="0000";b<="0000";a<="0100";
addr <= "01001100";
--a := band (ir, smask);
when "01001010" => amux<='0'; cond<="00"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="1001";a<="0011";
addr <= "00000000";
--sp := sp + a; goto 0;
when "01001011" => amux<='0'; cond<="11"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="0010";b<="1010";a<="0010";
addr <= "00000000";
--a := band (ir, smask);
when "01001100" => amux<='0'; cond<="00"; ula<="01";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="1001";a<="0011";
addr <= "00000000";
--a := inv (a);
when "01001101" => amux<='0'; cond<="00"; ula<="11";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="1010";a<="0000";
addr <= "00000000";
--a := a + 1; goto 75;
when "01001110" => amux<='0'; cond<="11"; ula<="00";sh<="00";mbr<='0';
mar<='0';rd<='0';wr<='0';enc<='1';c<="1010";b<="1010";a<="0110";
addr <= "01001011";
when others =>
end case;
end process combinacao_de_estados;
estado_clock: process (clk)
begin
if rising_edge (clk) then
if ((n='1' and cond(0)='1') or (z='1' and cond(1)='1') or (cond(1)='1' and cond(0)='1')) then
estado_atual <= addr;
else
estado_atual <= estado_atual + 1;
end if;
end if;
end process estado_clock;
end comportamental;
Decodificador4x16.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Decodificador4x16 is
port(entDec: in std_logic_vector(3 downto 0);
enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end Decodificador4x16;
architecture ComportamentoDec of Decodificador4x16 is
begin
process (entDec,enDec)
begin
sDec <= "0000000000000000";
if (enDec = '1') then
case entDec is
when "0000" => sDec <= "0000000000000001";
when "0001" => sDec <= "0000000000000010";
when "0010" => sDec <= "0000000000000100";
when "0011" => sDec <= "0000000000001000";
when "0100" => sDec <= "0000000000010000";
when "0101" => sDec <= "0000000000100000";
when "0110" => sDec <= "0000000001000000";
when "0111" => sDec <= "0000000010000000";
when "1000" => sDec <= "0000000100000000";
when "1001" => sDec <= "0000001000000000";
when "1010" => sDec <= "0000010000000000";
when "1011" => sDec <= "0000100000000000";
when "1100" => sDec <= "0001000000000000";
when "1101" => sDec <= "0010000000000000";
when "1110" => sDec <= "0100000000000000";
when "1111" => sDec <= "1000000000000000";
when others => null;
end case;
end if;
end process;
end ComportamentoDec;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchDecodificador4x16 is
end testBenchDecodificador4x16;
architecture testDecodificador4x16 of testBenchDecodificador4x16 is
component Decodificador4x16
port (entDec: in std_logic_vector(3 downto 0);
enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end component;
signal entDec:std_logic_vector (3 downto 0);
signal enDec:std_logic;
signal sDec:std_logic_vector(15 downto 0);
begin
comp:Decodificador4x16 port map (entDec,enDec,sDec);
process
begin
enDec <= '1';
entDec <= "0000","1111" after 2 ns,"0000" after 4 ns;
wait;
end process;
end testDecodificador4x16;
Decodificador4X16_estrutural.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Decodificador4x16_estrutural is
port(EntDec: in std_logic_vector(3 downto 0); enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end Decodificador4x16_estrutural;
architecture estrutural of Decodificador4x16_estrutural is
component AND5
port (E4,E3,E2,E1,E5:in std_logic; S: out std_logic);
end component;
component INV
port (E:in std_logic; S: out std_logic);
end component;
signal S1,S2,S3,S4: std_logic;
begin
P1: INV port map (EntDec(3),S1);
P2: INV port map (EntDec(2),S2);
P3: INV port map (EntDec(1),S3);
P4: INV port map (EntDec(0),S4);
--ENTRADAS ="0000" => SAIDA = "0000000000000001"
P5: AND5 port map (S1,S2,S3,S4,enDec,sDec(0));
--ENTRADAS ="0001"
P6: AND5 port map (S1,S2,S3,EntDec(0),enDec,sDec(1));
--ENTRADAS ="0010"
P7: AND5 port map (S1,S2,EntDec(1),S4,enDec,sDec(2));
--ENTRADAS ="0011"
P8: AND5 port map (S1,S2,EntDec(1),EntDec(0),enDec,sDec(3));
--ENTRADAS ="0100"
P9: AND5 port map (S1,EntDec(2),S3,S4,enDec,sDec(4));
--ENTRADAS ="0101"
P10: AND5 port map (S1,EntDec(2),S3,EntDec(0),enDec,sDec(5));
--ENTRADAS ="0110"
P11: AND5 port map (S1,EntDec(2),EntDec(1),S4,enDec,sDec(6));
--ENTRADAS ="0111"
P12: AND5 port map (S1,EntDec(2),EntDec(1),EntDec(0),enDec,sDec(7));
--ENTRADAS ="1000"
P13: AND5 port map (EntDec(3),S2,S3,S4,enDec,sDec(8));
--ENTRADAS ="1001"
P14: AND5 port map (EntDec(3),S2,S3,EntDec(0),enDec,sDec(9));
--ENTRADAS ="1010"
P15: AND5 port map (EntDec(3),S2,EntDec(1),S4,enDec,sDec(10));
--ENTRADAS ="1011"
P16: AND5 port map (EntDec(3),S2,EntDec(1),EntDec(0),enDec,sDec(11));
--ENTRADAS ="1100"
P17: AND5 port map (EntDec(3),EntDec(2),S3,S4,enDec,sDec(12));
--ENTRADAS ="1101"
P18: AND5 port map (EntDec(3),EntDec(2),S3,EntDec(0),enDec,sDec(13));
--ENTRADAS ="1110"
P19: AND5 port map (EntDec(3),EntDec(2),EntDec(1),S4,enDec,sDec(14));
--ENTRADAS ="1111"
P20: AND5 port map (EntDec(3),EntDec(2),EntDec(1),EntDec(0),enDec,sDec(15));
END estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchDecodificador4x16_estrutural is
end testBenchDecodificador4x16_estrutural;
architecture teste_estrutural of testBenchDecodificador4x16_estrutural is
component Decodificador4x16_estrutural
port (EntDec: in std_logic_vector(3 downto 0); enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end component;
signal sigEnt: std_logic_vector (3 downto 0);
signal sigEna: std_logic;
signal sigS: std_logic_vector (15 downto 0);
begin
comp: Decodificador4x16_estrutural port map (sigEnt,sigEna,sigS);
process
begin
sigEna <='0', '1' after 3 ns;
sigEnt <= "0000","1111" after 2 ns, "0000" after 4 ns, "0001" after 6 ns,"0010" after 8 ns,
"0011" after 10 ns, "0100" after 12 ns, "0101" after 14 ns, "0110" after 16 ns,
"0111" after 18 ns, "1000" after 20 ns, "1001" after 22 ns, "1010" after 24 ns,
"1011" after 28 ns, "1100" after 30 ns, "1101" after 32 ns, "1110" after 34 ns,
"1111" after 36 ns;
wait;
end process;
end teste_estrutural;
Decodificador4x16_fluxo.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Decodificador4x16_fluxo is
port(entDec: in std_logic_vector(3 downto 0);
enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end Decodificador4x16_fluxo;
architecture fluxoDec of Decodificador4x16_fluxo is
begin
--sDec <="0000000000000000";
--ENTRADAS ="0000" => SAIDA = "0000000000000001"
sDec(0) <= (NOT(entDec(3)) AND NOT(entDec(2)) AND NOT(entDec(1)) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="0001" => SAIDA = "0000000000000010"
sDec(1) <= (NOT(entDec(3)) AND NOT(entDec(2)) AND NOT(entDec(1)) AND entDec(0) AND enDec);
--ENTRADAS ="0010" => SAIDA = "0000000000000100"
sDec(2) <= (NOT(entDec(3)) AND NOT(entDec(2)) AND entDec(1) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="0011" => SAIDA = "0000000000001000"
sDec(3) <= (NOT(entDec(3)) AND NOT(entDec(2)) AND entDec(1) AND entDec(0) AND enDec);
--ENTRADAS ="0100" => SAIDA = "0000000000010000"
sDec(4) <= (NOT(entDec(3)) AND entDec(2) AND NOT(entDec(1)) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="0101" => SAIDA = "0000000000100000"
sDec(5) <= (NOT(entDec(3)) AND entDec(2) AND NOT(entDec(1)) AND entDec(0) AND enDec);
--ENTRADAS ="0110" => SAIDA = "0000000001000000"
sDec(6) <= (NOT(entDec(3)) AND entDec(2) AND entDec(1) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="0111" => SAIDA = "0000000010000000"
sDec(7) <= (NOT(entDec(3)) AND entDec(2) AND entDec(1) AND entDec(0) AND enDec);
--ENTRADAS ="1000" => SAIDA = "0000000100000000"
sDec(8) <= (entDec(3) AND NOT(entDec(2)) AND NOT(entDec(1)) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="1001" => SAIDA = "00000010000000000"
sDec(9) <= (entDec(3) AND NOT(entDec(2)) AND NOT(entDec(1)) AND entDec(0) AND enDec);
--ENTRADAS ="1010" => SAIDA = "00000100000000000"
sDec(10) <= (entDec(3) AND NOT(entDec(2)) AND entDec(1) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="1011" => SAIDA = "00001000000000000"
sDec(11) <= (entDec(3) AND NOT(entDec(2)) AND entDec(1) AND entDec(0) AND enDec);
--ENTRADAS ="1100" => SAIDA = "00010000000000000"
sDec(12) <= (entDec(3) AND entDec(2) AND NOT(entDec(1)) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="1101" => SAIDA = "00100000000000000"
sDec(13) <= (entDec(3) AND entDec(2) AND NOT(entDec(1)) AND entDec(0) AND enDec);
--ENTRADAS ="1110" => SAIDA = "01000000000000000"
sDec(14) <= (entDec(3) AND entDec(2) AND entDec(1) AND NOT(entDec(0)) AND enDec);
--ENTRADAS ="1111" => SAIDA = "10000000000000000"
sDec(15) <= (entDec(3) AND entDec(2) AND entDec(1) AND entDec(0) AND enDec);
end fluxoDec;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchDecodificador4x16_fluxo is
end testBenchDecodificador4x16_fluxo;
architecture teste of testBenchDecodificador4x16_fluxo is
component Decodificador4x16_fluxo
port (entDec: in std_logic_vector(3 downto 0);
enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end component;
signal sigEntDec: std_logic_vector (3 downto 0);
signal sigEnDec: std_logic;
signal signalSaidaDec: std_logic_vector (15 downto 0);
begin
comp: Decodificador4x16_fluxo port map (sigEntDec, sigEnDec, signalSaidaDec);
process
begin
sigEnDec <= '0','1' after 2 ns,'0' after 34 ns;
sigEntDec <= "0000","0001" after 4 ns,"0010" after 6 ns, "0011" after 8 ns,
"0100" after 10 ns,"0101" after 12 ns,"0110" after 14 ns,"0111" after 16 ns,"1000" after 18 ns,
"1001" after 20 ns,"1010" after 22 ns,"1011" after 24 ns,"1100" after 26 ns,"1101" after 28 ns,
"1110" after 30 ns,"1111" after 32 ns;
-- sigEntDec <= "0000","1111" after 4 ns;
wait;
end process;
end teste;
Deslocador_Algoritmica.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Deslocador_algoritmica is
port(EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end Deslocador_algoritmica;
architecture algoritmica of Deslocador_algoritmica is
begin
process (EntA,EntF)
begin
case EntF is
when "00" => SaiS <= EntA; --mantém
when "01" => SaiS <= to_stdlogicvector(to_bitvector(EntA) srl 1) ;--desloca 1 bit para a direita
when "10" => SaiS <= to_stdlogicvector(to_bitvector(EntA) sll 1); -- desloca 1 bit para a esquerda
--when "11" => S <= A;
when others => null;
end case;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchDeslocador_algoritimica is
end testbenchDeslocador_algoritimica;
architecture teste of testbenchDeslocador_algoritimica is
component Deslocador_algoritmica
port (EntA:in std_logic_vector (15 downto 0);
EntF:in std_logic_vector (1 downto 0);
SaiS:out std_logic_vector (15 downto 0));
end component;
signal sigA,sigS: std_logic_vector(15 downto 0);
signal sigF: std_logic_vector(1 downto 0);
begin
comp: Deslocador_algoritmica port map (sigA,sigF,sigS);
process
begin
sigA<="0000000000000000","1111111111111111" after 2 ns;
sigF<="00","01" after 4 ns,"11" after 6 ns, "10" after 8 ns;
wait;
end process;
end teste;
Deslocador_Estrutural.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Deslocador_estrutural is
port(EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end Deslocador_estrutural;
architecture Deslocador_estrutural of Deslocador_estrutural is
component AND2
port (E2,E1:in std_logic; S: out std_logic);
end component;
component INV
port (E: in std_logic; S: out std_logic);
end component;
component OR2
port (E1,E2:in std_logic; S: out std_logic);
end component;
component AND3
port (E1,E2,E3:in std_logic; S: out std_logic);
end component;
component OR3
port (E1,E2,E3:in std_logic; S: out std_logic);
end component;
signal S1,S2,S3,S4,S5,S6,S7,S8: std_logic;
signaL S10,S11,S12,S14,S15,S16: std_logic;
signal S18,S19,S20,S22,S23,S24: std_logic;
signal S26,S27,S28,S30,S31,s32: std_logic;
signal S34,S35,S36,S38,S39,S40: std_logic;
signal S42,S43,S44,S46,S47,S48: std_logic;
signal S50,S51,S52,S54,S55,S56: std_logic;
signal S58,S59,S60,S62,S63,S64: std_logic;
signal S66,S67: std_logic;
begin
P1: INV port map (EntF(0), S1);
P2: INV port map (EntF(1), S2);
P3: AND2 port map (S1,EntF(1),S3);
P4: AND2 port map (S2,EntF(0),S4);
P5: OR2 port map (S3,S4,S5);
P6:INV port map (S5, S6);
--lOGICA DA SAIDA 0
P7: AND2 port map (S6,EntA(0),S7);
P8: AND2 port map (S4,EntA(1),S8);
P9: OR2 port map (S7,S8,SaiS(0));
--lOGICA DA SAIDA 1
P10: AND2 port map (S3,EntA(0),S10);
P11: AND2 port map (S6,EntA(1),S11);
P12: AND2 port map (S4,EntA(2),S12);
P13: OR3 port map (S10,S11,S12,SaiS(1));
--lOGICA DA SAIDA 2
P14: AND2 port map (S3,EntA(1),S14);
P15: AND2 port map (S6,EntA(2),S15);
P16: AND2 port map (S4,EntA(3),S16);
P17: OR3 port map (S14,S15,S16,SaiS(2));
--lOGICA DA SAIDA 3
P18: AND2 port map (S3,EntA(2),S18);
P19: AND2 port map (S6,EntA(3),S19);
P20: AND2 port map (S4,EntA(4),S20);
P21: OR3 port map (S18,S19,S20,SaiS(3));
--lOGICA DA SAIDA 4
P22: AND2 port map (S3,EntA(3),S22);
P23: AND2 port map (S6,EntA(4),S23);
P24: AND2 port map (S4,EntA(5),S24);
P25: OR3 port map (S22,S23,S24,SaiS(4));
--lOGICA DA SAIDA 5
P26: AND2 port map (S3,EntA(4),S26);
P27: AND2 port map (S6,EntA(5),S27);
P28: AND2 port map (S4,EntA(6),S28);
P29: OR3 port map (S26,S27,S28,SaiS(5));
--lOGICA DA SAIDA 6
P30: AND2 port map (S3,EntA(5),S30);
P31: AND2 port map (S6,EntA(6),S31);
P32: AND2 port map (S4,EntA(7),S32);
P33: OR3 port map (S30,S31,S32,SaiS(6));
--lOGICA DA SAIDA 7
P34: AND2 port map (S3,EntA(6),S34);
P35: AND2 port map (S6,EntA(7),S35);
P36: AND2 port map (S4,EntA(8),S36);
P37: OR3 port map (S34,S35,S36,SaiS(7));
--lOGICA DA SAIDA 8
P38: AND2 port map (S3,EntA(7),S38);
P39: AND2 port map (S6,EntA(8),S39);
P40: AND2 port map (S4,EntA(9),S40);
P41: OR3 port map (S38,S39,S40,SaiS(8));
--lOGICA DA SAIDA 9
P42: AND2 port map (S3,EntA(8),S42);
P43: AND2 port map (S6,EntA(9),S43);
P44: AND2 port map (S4,EntA(10),S44);
P45: OR3 port map (S42,S43,S44,SaiS(9));
--lOGICA DA SAIDA 10
P46: AND2 port map (S3,EntA(9),S46);
P47: AND2 port map (S6,EntA(10),S47);
P48: AND2 port map (S4,EntA(11),S48);
P49: OR3 port map (S46,S47,S48,SaiS(10));
--lOGICA DA SAIDA 11
P50: AND2 port map (S3,EntA(10),S50);
P51: AND2 port map (S6,EntA(11),S51);
P52: AND2 port map (S4,EntA(12),S52);
P53: OR3 port map (S50,S51,S52,SaiS(11));
--lOGICA DA SAIDA 12
P54: AND2 port map (S3,EntA(11),S54);
P55: AND2 port map (S6,EntA(12),S55);
P56: AND2 port map (S4,EntA(13),S56);
P57: OR3 port map (S54,S55,S56,SaiS(12));
--lOGICA DA SAIDA 13
P58: AND2 port map (S3,EntA(12),S58);
P59: AND2 port map (S6,EntA(13),S59);
P60: AND2 port map (S4,EntA(14),S60);
P61: OR3 port map (S58,S59,S60,SaiS(13));
--lOGICA DA SAIDA 14
P62: AND2 port map (S3,EntA(13),S62);
P63: AND2 port map (S6,EntA(14),S63);
P64: AND2 port map (S4,EntA(15),S64);
P65: OR3 port map (S62,S63,S64,SaiS(14));
--lOGICA DA SAIDA 15
P66: AND2 port map (S3,EntA(14),S66);
P67: AND2 port map (S6,EntA(15),S67);
P68: OR2 port map (S66,S67,SaiS(15));
end Deslocador_estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchDeslocador_estrutural is
end testBenchDeslocador_estrutural;
architecture teste_estrutural of testBenchDeslocador_estrutural is
component Deslocador_estrutural
port (EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end component;
signal sigEntA: std_logic_vector (15 downto 0);
signal sigEntF: std_logic_vector(1 downto 0);
signal sigSaiS: std_logic_vector (15 downto 0);
begin
comp: Deslocador_estrutural port map (sigEntA,sigEntF,sigSaiS);
process
begin
sigEntA <= "1111111111111111","1111111111111110" after 14 ns;
sigEntF <= "00", "01" after 4 ns,"11" after 8 ns,"10" after 12 ns,
"00" after 16 ns,"01" after 20 ns,"11" after 24 ns,"10" after 28 ns;
wait;
end process;
end teste_estrutural;
Deslocador_Fluxo.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Deslocador_Fluxo is
port(EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end Deslocador_Fluxo;
architecture fluxoDeslocador of Deslocador_Fluxo is
begin
SaiS(0) <= ((not((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(1)) or (EntF(0) and not(EntF(1)) and EntA(1)));
SaiS(1) <= ((not(EntF(0)) and EntF(1) and EntA(2)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(1)) or (EntF(0) and not(EntF(1)) and EntA(0)));
SaiS(2) <= ((not(EntF(0)) and EntF(1) and EntA(3)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(2)) or (EntF(0) and not(EntF(1)) and EntA(1)));
SaiS(3) <= ((not(EntF(0)) and EntF(1) and EntA(4)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(3)) or (EntF(0) and not(EntF(1)) and EntA(2)));
SaiS(4) <= ((not(EntF(0)) and EntF(1) and EntA(5)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(4)) or (EntF(0) and not(EntF(1)) and EntA(3)));
SaiS(5) <= ((not(EntF(0)) and EntF(1) and EntA(6)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(5)) or (EntF(0) and not(EntF(1)) and EntA(4)));
SaiS(6) <= ((not(EntF(0)) and EntF(1) and EntA(7)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(6)) or (EntF(0) and not(EntF(1)) and EntA(5)));
SaiS(7) <= ((not(EntF(0)) and EntF(1) and EntA(8)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(7)) or (EntF(0) and not(EntF(1)) and EntA(6)));
SaiS(8) <= ((not(EntF(0)) and EntF(1) and EntA(9))
or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(8)) or (EntF(0) and not(EntF(1)) and EntA(7)));
SaiS(9) <= ((not(EntF(0)) and EntF(1) and EntA(10)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(9)) or (EntF(0) and not(EntF(1)) and EntA(8)));
SaiS(10) <= ((not(EntF(0)) and EntF(1) and EntA(11)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(10)) or (EntF(0) and not(EntF(1)) and EntA(9)));
SaiS(11) <= ((not(EntF(0)) and EntF(1) and EntA(12)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(11)) or (EntF(0) and not(EntF(1)) and EntA(10)));
SaiS(12) <= ((not(EntF(0)) and EntF(1) and EntA(13)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(12)) or (EntF(0) and not(EntF(1)) and EntA(11)));
SaiS(13) <= ((not(EntF(0)) and EntF(1) and EntA(14)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(13)) or (EntF(0) and not(EntF(1)) and EntA(12)));
SaiS(14) <= ((not(EntF(0)) and EntF(1) and EntA(15)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(14)) or (EntF(0) and not(EntF(1)) and EntA(13)));
SaiS(15) <= ((not(EntF(0)) and EntF(1) and EntA(15)) or (not ((not(EntF(0)) and EntF(1)) or (EntF(0) and not(EntF(1)))) and EntA(14)));
end fluxoDeslocador;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchDeslocador_fluxo is
end testBenchDeslocador_fluxo;
architecture teste of testBenchDeslocador_fluxo is
component Deslocador_Fluxo
port (EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end component;
signal sigEntA: std_logic_vector (15 downto 0);
signal sigEntF: std_logic_vector (1 downto 0);
signal signalSaiS: std_logic_vector (15 downto 0);
begin
comp: Deslocador_Fluxo port map (sigEntA, sigEntF, signalSaiS);
process
begin
sigEntA<="0000000000000000","1111111111111111" after 2 ns;
sigEntF<="00","01" after 4 ns,"11" after 6 ns, "10" after 8 ns;
wait;
end process;
end teste;
FlipFlopD.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ffD is
port(RST,CLK:in bit;
D: in std_logic;
Q,NQ: out std_logic);
end ffD;
architecture algoritmica of ffD is
begin
process (RST,D,CLK) begin
if ( RST = '1' ) then
Q<= '0';
NQ <= '1';
elsif ( CLK = '1' and CLK'event ) then
Q <= D;
NQ <= not D;
end if;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity teste_ffD is
end teste_ffD;
architecture teste of teste_ffD is
component ffD
port(RST,CLK:in bit;
D: in std_logic;
Q,NQ: out std_logic);
end component;
signal sigRST, sigCLK: bit;
signal sigD,sigQ,sigNQ :std_logic ;
begin
comp:ffD port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
process
begin
sigCLK <='0', not (sigCLK) after 3 ns;
sigD<='0','1' after 2 ns;
wait for 6 ns;
end process;
end teste;
GSC.vhd
library ieee;
use ieee.std_logic_1164.all;
entity GSC is
port(T1,T2,T3,T4: out std_logic);
end GSC;
architecture comportamental of GSC is
signal clock: std_logic:='1';
signal sigT1: std_logic:='1';
signal sigT2: std_logic:='1';
signal sigT3: std_logic:='1';
signal sigT4: std_logic:='1';
begin
process
begin
clock <= not clock after 5 ns;
wait for 5 ns;
end process;
process(clock)
begin
if clock'event and clock='1'
then sigT1<='1', '0' after 2.5 ns;
end if;
end process;
process(sigT1)
begin
if sigT1'event and sigT1='0'
then sigT2<='1', '0' after 2.5 ns;
end if;
end process;
process(sigT2)
begin
if sigT2'event and sigT2='0'
then sigT3<='1', '0' after 2.5 ns;
end if;
end process;
process(sigT3)
begin
if sigT3'event and sigT3='0'
then sigT4<='1', '0' after 2.5 ns;
end if;
end process;
T1 <= sigT1;
T2 <= sigT2;
T3 <= sigT3;
T4 <= sigT4;
end comportamental;
incrementadorGen.vhd
library ieee;
use ieee.std_logic_1164.all;
entity incrementadorGen is
generic (tam: integer);
port (A: in std_logic_vector (tam - 1 downto 0);
resultado: out std_logic_vector(tam - 1 downto 0));
end incrementadorGen;
architecture estrutura of incrementadorGen is
component somador is
port (A, B, vem1: in std_logic;
resultado, vai1: out std_logic);
end component;
signal result: std_logic_vector (tam - 1 downto 0);
signal b: std_logic_vector (31 downto 0);
signal vem1: std_logic_vector (tam + 1 downto 0);
begin
b <= "00000000000000000000000000000000";
vem1(0)<='1';
som: for i in tam - 1 downto 0 generate
somn: somador port map (a(i),b(i),vem1(i),result(i),vem1(i+1));
end generate;
resultado <= result;
end estrutura;
library ieee;
use ieee.std_logic_1164.all;
entity testbench_incrementadorGen is
end testbench_incrementadorGen;
architecture testbench of testbench_incrementadorGen is
component incrementadorGen is
generic (tam: integer);
port (A: in std_logic_vector (tam - 1 downto 0);
resultado: out std_logic_vector(tam - 1 downto 0));
end component;
signal sigA,sigResultado: std_logic_vector (3 downto 0);
begin
incrementadorX: incrementadorGen generic map (4) port map (sigA,sigResultado);
process
begin
sigA<= "0000", "0001" after 5 ns, "0010" after 10 ns, "1111" after 20 ns;
wait;
end process;
end testbench;
Latch.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Latch is
port(
D: in std_logic_vector(15 downto 0);
CK: in std_logic;
Q: out std_logic_vector(15 downto 0)
);
end Latch;
architecture algoritmica of Latch is
begin
process (D,CK)
begin
if CK ='1' and CK'event then
Q<=D;
end if;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity testbench_latch is
end testbench_latch;
architecture testbench of testbench_latch is
component Latch is
generic (tam: integer);
port (en: in std_logic_vector (tam - 1 downto 0);
comando: in std_logic;
saida: out std_logic_vector (tam - 1 downto 0));
end component;
signal a, b: std_logic_vector (7 downto 0);
signal comando: std_logic;
begin
Latcha: Latch generic map (8) port map (a,comando,b);
process
begin
a <= "00110011", "00001111" after 10 ns, "10101010" after 20 ns;
comando <= '0', '1' after 5 ns, '0' after 15 ns, '1' after 30 ns;
wait;
end process;
end testbench;
Logica_Microsequenciamento_Algoritmica.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Logica_microsequenciamento_algoritmica is
port(EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end Logica_microsequenciamento_algoritmica;
architecture algoritmica of Logica_microsequenciamento_algoritmica is
begin
process (EntN,EntZ,EntCond)
begin
-- SaiS <= ((not(EntCond(1)) and EntCond(0) and EntN) or (EntCond(1) and not(EntCond(0)) and EntZ)
-- or (EntCond(1) and EntCond(0));
SaiS <= ((EntCond(0) and EntN) or (EntCond(1) and EntZ) or (EntCond(1) and EntCond(0)));
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchLogica_microsequenciamento_algoritimica is
end testbenchLogica_microsequenciamento_algoritimica;
architecture teste of testbenchLogica_microsequenciamento_algoritimica is
component Logica_microsequenciamento_algoritmica
port (EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end component;
signal sigEntN,sigEntZ,sigSaiS: std_logic;
signal sigEntCond: std_logic_vector(1 downto 0);
begin
comp: Logica_microsequenciamento_algoritmica port map (sigEntN,sigEntZ,sigEntCond,sigSaiS);
process
begin
-- a saída só deve ser 1 nos seguintes casos:
-- quando Cond =01 e N=1;
-- quando Cond =11 e Z=1;
sigEntN <= '0','1' after 2ns, '0' after 6 ns,'1' after 12ns, '0' after 16 ns,
'1' after 22ns, '0' after 26 ns,'1' after 32ns, '0' after 36 ns;
sigEntZ <= '0','1' after 4ns, '0' after 8 ns,'1' after 14ns, '0' after 18 ns,
'1' after 24ns, '0' after 28 ns,'1' after 34ns, '0' after 38 ns;
sigEntCond <= "00", "01" after 10ns , "10" after 20 ns,"11" after 30 ns;
wait;
end process;
end teste;
Logica_Microsequenciamento_Estrutural.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Logica_microsequenciamento_estrutural is
port(EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end Logica_microsequenciamento_estrutural;
architecture Logica_microsequenciamento_estrutural of Logica_microsequenciamento_estrutural is
component AND2
port (E2,E1:in std_logic; S: out std_logic);
end component;
component OR3
port (E1,E2,E3:in std_logic; S: out std_logic);
end component;
signal S1,S2,S3: std_logic;
begin
P1: AND2 port map (EntN,EntCond(0),S1);
P2: AND2 port map (EntZ,EntCond(1),S2);
P3: AND2 port map (EntCond(0),EntCond(1),S3);
P4: OR3 port map (S1,S2,S3,SaiS);
end Logica_microsequenciamento_estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchLogica_microsequenciamento_estrutural is
end testBenchLogica_microsequenciamento_estrutural;
architecture teste_estrutural of testBenchLogica_microsequenciamento_estrutural is
component Logica_microsequenciamento_estrutural
port (EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end component;
signal sigEntN,sigEntZ,sigSaiS: std_logic;
signal sigEntCond: std_logic_vector(1 downto 0);
begin
comp: Logica_microsequenciamento_estrutural port map (sigEntN,sigEntZ,sigEntCond,sigSaiS);
process
begin
sigEntN <= '0','1' after 2ns, '0' after 6 ns,'1' after 12ns, '0' after 16 ns,
'1' after 22ns, '0' after 26 ns,'1' after 32ns, '0' after 36 ns;
sigEntZ <= '0','1' after 4ns, '0' after 8 ns,'1' after 14ns, '0' after 18 ns,
'1' after 24ns, '0' after 28 ns,'1' after 34ns, '0' after 38 ns;
sigEntCond <= "00", "01" after 10ns , "10" after 20 ns,"11" after 30 ns;
wait;
end process;
end teste_estrutural;
Logica_Microsequenciamento_Fluxo.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Logica_microsequenciamento_Fluxo is
port(EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end Logica_microsequenciamento_Fluxo;
architecture fluxoLogica_microsequenciamento of Logica_microsequenciamento_Fluxo is
begin
SaiS <= ((EntCond(0) AND EntN) OR (EntCond(1) AND EntZ) OR (EntCond(0) AND EntCond(1)));
end fluxoLogica_microsequenciamento;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchLogica_microsequenciamento_fluxo is
end testBenchLogica_microsequenciamento_fluxo;
architecture teste of testBenchLogica_microsequenciamento_fluxo is
component Logica_microsequenciamento_Fluxo
port (EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end component;
signal sigEntN,sigEntZ,signalSaiS: std_logic;
signal sigEntCond: std_logic_vector (1 downto 0);
begin
comp: Logica_microsequenciamento_Fluxo port map (sigEntN,sigEntZ, sigEntCond, signalSaiS);
process
begin
-- a saída só deve ser 1 nos seguintes casos:
-- quando Cond =01 e N=1;
-- quando Cond =11 e Z=1;
sigEntN <= '0','1' after 2ns, '0' after 6 ns,'1' after 12ns, '0' after 16 ns,
'1' after 22ns, '0' after 26 ns,'1' after 32ns, '0' after 36 ns;
sigEntZ <= '0','1' after 4ns, '0' after 8 ns,'1' after 14ns, '0' after 18 ns,
'1' after 24ns, '0' after 28 ns,'1' after 34ns, '0' after 38 ns;
sigEntCond <= "00", "01" after 10ns , "10" after 20 ns,"11" after 30 ns;
wait;
end process;
end teste;
memoriaT3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity memoriaT3 is
port (signal bc, csa, csb, csc: in std_logic_vector(15 downto 0);
signal sclock4: in std_logic;
signal ba, bb: out std_logic_vector(15 downto 0));
end memoriaT3;
architecture estrutura of memoriaT3 is
component tristate is
port ( entrada: in std_logic_vector (15 downto 0);
oe: in std_logic;
saida: out std_logic_vector (15 downto 0));
end component ;
component registrador is
generic (nbits: integer);
port ( dado: in std_logic_vector (nbits - 1 downto 0);
clk: in std_logic;
saida: out std_logic_vector (nbits - 1 downto 0));
end component;
signal barramentoA, barramentoB, clk_reg: std_logic_vector (15 downto 0);
signal comando, rd: std_logic;
signal saida0, saida1, saida2, saida3, saida4, saida5, saida6, saida7,
saida8, saida9, saida10, saida11, saida12, saida13, saida14, saida15: std_logic_vector (15 downto 0);
signal s_0:std_logic_vector(15 downto 0):=x"0000";
signal s_1:std_logic_vector(15 downto 0):=x"0001";
signal s_11:std_logic_vector(15 downto 0):=x"FFFF";
signal s_amask:std_logic_vector(15 downto 0):=x"03FF";
signal s_smask:std_logic_vector(15 downto 0):=x"00FF";
begin
clkreg: for i in 0 to 15 generate
clk_reg (i) <= csc(i) and sclock4;
end generate;
PC: registrador generic map (16) port map (bc,clk_reg(0),saida0);
tripca: tristate port map (saida0,csa(0),barramentoA);
tripcb: tristate port map (saida0,csb(0),barramentoB);
AC: registrador generic map (16) port map (bc,clk_reg(1),saida1);
triaca: tristate port map (saida1,csa(1),barramentoA);
triacb: tristate port map (saida1,csb(1),barramentoB);
SP: registrador generic map (16) port map (bc,clk_reg(2),saida2);
trispa: tristate port map (saida2,csa(2),barramentoA);
trispb: tristate port map (saida2,csb(2),barramentoB);
IR: registrador generic map (16) port map (bc,clk_reg(3),saida3);
triIRa: tristate port map (saida3,csa(3),barramentoA);
triirb: tristate port map (saida3,csb(3),barramentoB);
TIR: registrador generic map (16) port map (bc,clk_reg(4),saida4);
tritIRa: tristate port map (saida4,csa(4),barramentoA);
tritirb: tristate port map (saida4,csb(4),barramentoB);
REG0: registrador generic map (16) port map (s_0,sclock4,saida5);
tri0a: tristate port map (saida5,csa(5),barramentoA);
tri0b: tristate port map (saida5,csb(5),barramentoB);
REGM1: registrador generic map (16) port map (s_1,sclock4,saida6);
triM1a: tristate port map (saida6,csa(6),barramentoA);
triM1b: tristate port map (saida6,csb(6),barramentoB);
REGm11: registrador generic map (16) port map (s_11,sclock4,saida7);
trim11a: tristate port map (saida7,csa(7),barramentoA);
trim11b: tristate port map (saida7,csb(7),barramentoB);
AMASK: registrador generic map (16) port map (s_amask,sclock4,saida8);
triAMASKa: tristate port map (saida8,csa(8),barramentoA);
triAMASKb: tristate port map (saida8,csb(8),barramentoB);
SMASK: registrador generic map (16) port map (s_smask,sclock4,saida9);
triSMASKa: tristate port map (saida9,csa(9),barramentoA);
triSMASKb: tristate port map (saida9,csb(9),barramentoB);
A: registrador generic map (16) port map (bc,clk_reg(10),saida10);
triAa: tristate port map (saida10,csa(10),barramentoA);
triAb: tristate port map (saida10,csb(10),barramentoB);
B: registrador generic map (16) port map (bc,clk_reg(11),saida11);
triBa: tristate port map (saida11,csa(11),barramentoA);
triBb: tristate port map (saida11,csb(11),barramentoB);
C: registrador generic map (16) port map (bc,clk_reg(12),saida12);
triCa: tristate port map (saida12,csa(12),barramentoA);
triCb: tristate port map (saida12,csb(12),barramentoB);
D: registrador generic map (16) port map (bc,clk_reg(13),saida13);
triDa: tristate port map (saida13,csa(13),barramentoA);
triDb: tristate port map (saida13,csb(13),barramentoB);
E: registrador generic map (16) port map (bc,clk_reg(14),saida14);
triEa: tristate port map (saida14,csa(14),barramentoA);
triEb: tristate port map (saida14,csb(14),barramentoB);
F: registrador generic map (16) port map (bc,clk_reg(15),saida15);
triFa: tristate port map (saida15,csa(15),barramentoA);
triFb: tristate port map (saida15,csb(15),barramentoB);
ba <= barramentoA;
bb <= barramentoB;
end estrutura;
Memoria_controle.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity Memoria_Controle is
port(Address: in unsigned (7 downto 0);
Dado: out std_logic_vector (31 downto 0));
end Memoria_Controle;
architecture algoritmica of Memoria_Controle is
type TP_Memoria is array (0 to 73) of std_logic_vector (31 downto 0);
constant Memoria: TP_Memoria := ("00000000110000000000000000000000", -- 0
"00000000010100000110000000000000", -- 1
"10001000000110101000000000000000", -- 2
"10110000000100110000000000011101", -- 3
"00010100000101000000001100000000", -- 4
"00110100000101000000010000010100", -- 5
"00110100000101000000010000001110", -- 6
"00110000000101000000010000001011", -- 7
"00000000110000001010000000000000", -- 8
"00000000010000000000000000000000", -- 9
"11110000000100010000000000000000", -- 10
"00010001100000001010000100000000", -- 11
"00000000001000000000000000000000", -- 12
"01100000001000000000000000000000", -- 13
"00000000110000001010000000000000", -- 14
"00110000010101000000010000010001", -- 15
"11100000000100010001000000000000", -- 16
"10011000000110100000000000000000", -- 17
"00000000000110101010011000000000", -- 18
"01100000000100010001101000000000", -- 19
"00110100000101000000010000011010", -- 20
"00110000000101000000010000011000", -- 21
"00110000000100010000000100000000", -- 22
"01100000000000000000000000011011", -- 23
"01010000000100010000000100011011", -- 24
"01100000000000000000000000000000", -- 25
"00110000000101000000010000011100", -- 26
"01110000000100000000101000000000", -- 27
"01110000000100010000101000000000", -- 28
"00110100000101000000010000011111", -- 29
"01100000000110101010001000000110", -- 30
"00110100000101000000010000100101", -- 31
"00110000000101000000010000100011", -- 32
"00110000000100010000000100011011", -- 33
"01100000000000000000000000000000", -- 34
"01010000000100010000000100000000", -- 35
"01100000000000000000000000011011", -- 36
"00110100000101000000010000101010", -- 37
"00000000000100100111001000000000", -- 38
"00010001100000000010000000000000", -- 39
"00010000001100000000101000000000", -- 40
"01100000001000000000000000000000", -- 41
"00110100000101000000010000111101", -- 42
"00110100000101000000010000110101", -- 43
"00110000000101000000010000110001", -- 44
"00000000110000000001000000000000", -- 45
"00000000010100100010011100000000", -- 46
"00000000101000000010000000000000", -- 47
"01100000001000000000000000000000", -- 48
"00000000110000000010000000000000", -- 49
"00000000010100100010011000000000", -- 50
"00000000101000000001000000000000", -- 51
"01100000001000000000000000000000", -- 52
"00110000000101000000010000111010", -- 53
"00000000000100100010011100000000", -- 54
"00010001100000000010000100000000", -- 55
"00000000001000000000000000000000", -- 56
"01100000001000000000000000000000", -- 57
"00000000110000000010000000000000", -- 58
"00000000010100100010011000000000", -- 59
"11110000000100010000000000000000", -- 60
"00110100000101000000010001000101", -- 61
"00110000000101000000010001000010", -- 62
"00000000110000000010000000000000", -- 63
"00000000010100100010011000000000", -- 64
"11110000000100000000000000000000", -- 65
"00010000000110100000000100000000", -- 66
"00010000000100010000001000000000", -- 67
"00010000000100100000101000000000", -- 68
"00000000000110100011100100000000", -- 69
"00110000000101000000010001001000", -- 70
"01100000000100100010101000000000", -- 71
"00011000000110100000101000000000", -- 72
"01100000000110101010011001000111"); -- 73
begin
process (Address)
begin
Dado <= Memoria(to_integer(Address));
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_bit.all;
entity TestBench_MC is
end TestBench_MC;
architecture test of TestBench_MC is
component Memoria_Controle
port(Address: in unsigned (7 downto 0); Dado: out std_logic_vector (31 downto 0));
end component;
signal SigAdd: unsigned(7
downto 0);
signal SigDado: std_logic_vector(31 downto 0);
begin
MC: Memoria_Controle port map (SigAdd, SigDado);
process
begin
SigAdd <="00000000",
"00000001" after 1 ns,
"00000010" after 2 ns,
"00000011" after 3 ns,
"00000100" after 4 ns,
"00000101" after 5 ns,
"00000110" after 6 ns,
"00000111" after 7 ns,
"00001000" after 8 ns,
"00001001" after 9 ns,
"00001010" after 10 ns,
"00001011" after 11 ns,
"00001100" after 12 ns,
"00001101" after 13 ns,
"00001110" after 14 ns,
"00001111" after 15 ns,
"00010000" after 16 ns,
"00010001" after 17 ns,
"00010010" after 18 ns,
"00010011" after 19 ns,
"00010100" after 20 ns,
"00010101" after 21 ns,
"00010110" after 22 ns,
"00010111" after 23 ns,
"00011000" after 24 ns,
"00011001" after 25 ns,
"00011010" after 26 ns,
"00011011" after 27 ns,
"00011100" after 28 ns,
"00011101" after 29 ns,
"00011110" after 30 ns,
"00011111" after 31 ns,
"00100000" after 32 ns,
"00100001" after 33 ns,
"00100010" after 34 ns,
"00100011" after 35 ns,
"00100100" after 36 ns,
"00100101" after 37 ns,
"00100110" after 38 ns,
"00100111" after 39 ns,
"00101000" after 40 ns,
"00101001" after 41 ns,
"00101010" after 42 ns,
"00101011" after 43 ns,
"00101100" after 44 ns,
"00101101" after 45 ns,
"00101110" after 46 ns,
"00101111" after 47 ns,
"00110000" after 48 ns,
"00110001" after 49 ns,
"00110010" after 50 ns,
"00110011" after 51 ns,
"00110100" after 52 ns,
"00110101" after 53 ns,
"00110110" after 54 ns,
"00110111" after 55 ns,
"00111000" after 56 ns,
"00111001" after 57 ns,
"00111010" after 58 ns,
"00111011" after 59 ns,
"00111100" after 60 ns,
"00111101" after 61 ns,
"00111110" after 62 ns,
"00111111" after 63 ns,
"01000000" after 64 ns,
"01000001" after 65 ns,
"01000010" after 66 ns,
"01000011" after 67 ns,
"01000100" after 68 ns,
"01000101" after 69 ns,
"01000110" after 70 ns,
"01000111" after 71 ns,
"01001000" after 72 ns,
"01001001" after 73 ns;
wait;
end process;
end test;
MUX2x1 - Estrutural.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity MUX2x1_estrutural is
port (A,B,C:in std_logic; S:out std_logic);
end MUX2x1_estrutural ;
architecture estrutural of MUX2x1_estrutural is
component AND2
port (E1,E2:in std_logic; S: out std_logic);
end component;
component INV
port (E: in std_logic; S: out std_logic);
end component;
component OR2
port (E1,E2:in std_logic; S: out std_logic);
end component;
signal S1,S2,S3: std_logic;
begin
P1: AND2 port map (B,C,S1);
P2: INV port map (C,S2);
P3: AND2 port map (S2,A,S3);
P4: OR2 port map (S1,S3,S);
END estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testBenchMUX2x1_estrutural is
end testBenchMUX2x1_estrutural;
architecture teste_estrutural of testBenchMUX2x1_estrutural is
component MUX2x1_estrutural
port (A,B,C:in std_logic; S:out std_logic);
end component;
signal sigA,sigB,sigC,sigS:std_logic;
begin
comp: MUX2x1_estrutural
port map (sigA,sigB,sigC,sigS);
process
begin
sigA <= '0','1' after 2 ns, '0' after 4 ns;
sigB <= '1','0' after 3 ns, '1' after 5 ns;
sigC <= '0','1' after 3 ns, '0' after 6 ns;
wait;
end process;
end teste_estrutural;
Mux2x1_16.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux2x1_16 is
port (A,B:in std_logic_vector (15 downto 0);
C: in std_logic;
S:out std_logic_vector (15 downto 0));
end mux2x1_16;
architecture estrutural of mux2x1_16 is
component mux2x1
port (A,B,C: in std_logic; S:out std_logic);
end component;
begin
M15:mux2x1 port map (A(15),B(15),C,S(15));
M14:mux2x1 port map (A(14),B(14),C,S(14));
M13:mux2x1 port map (A(13),B(13),C,S(13));
M12:mux2x1 port map (A(12),B(12),C,S(12));
M11:mux2x1 port map (A(11),B(11),C,S(11));
M10:mux2x1 port map (A(10),B(10),C,S(10));
M09:mux2x1 port map (A(9),B(9),C,S(9));
M08:mux2x1 port map (A(8),B(8),C,S(8));
M07:mux2x1 port map (A(7),B(7),C,S(7));
M06:mux2x1 port map (A(6),B(6),C,S(6));
M05:mux2x1 port map (A(5),B(5),C,S(5));
M04:mux2x1 port map (A(4),B(4),C,S(4));
M03:mux2x1 port map (A(3),B(3),C,S(3));
M02:mux2x1 port map (A(2),B(2),C,S(2));
M01:mux2x1 port map (A(1),B(1),C,S(1));
M00:mux2x1 port map (A(0),B(0),C,S(0));
end estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchMUX2X1_16 is
end testbenchMUX2X1_16;
architecture teste of testbenchMUX2X1_16 is
component MUX2X1_16
port (A,B:in std_logic_vector (15 downto 0);C: in std_logic;
S:out std_logic_vector (15 downto 0));
end component;
signal sigA,sigB,sigS:std_logic_vector (15 downto 0);
signal sigC:std_logic;
begin
comp:MUX2X1_16 port map (sigA,sigB,sigC,sigS);
process
begin
sigA<="0000000000000000","1111111111111111" after 2 ns,"0000000000000000" after 4 ns;
sigB<="1111111111111111","0000000000000000" after 3 ns,"1111111111111111" after 5 ns;
sigC<='0','1' after 3 ns,'0' after 6 ns;
wait;
end process;
end teste;
Mux2x1_algoritmica.vhd
library ieee;
use ieee.std_logic_1164.all;
entity MUX2x1 is
port (A, B, C: in std_logic;
S: out std_logic);
end MUX2x1;
architecture algoritmica of MUX2x1 is
begin
process (A, B, C)
begin
if C='0' then
S<=A;
else S<=B;
end if;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchMUX2x1_algoritimica is
end testbenchMUX2x1_algoritimica;
architecture teste of testbenchMUX2x1_algoritimica is
component MUX2x1
port (A, B, C: in std_logic;
S: out std_logic);
end component;
signal sigA, sigB, sigC, sigS: std_logic;
begin
comp: MUX2x1 port map (sigA, SigB, sigC, sigS);
process
begin
sigA <= '0','1' after 2 ns,'0' after 4 ns;
sigB <= '1','0' after 3 ns,'1' after 5 ns;
sigC <= '0','1' after 3 ns,'0' after 6 ns;
wait;
end process;
end teste;
MUX2X1_Fluxo.vhd
library ieee;
use ieee.std_logic_1164.all;
entity MUX2x1_fluxo is
port (A, B, C: in std_logic;
S: out std_logic);
end MUX2x1_fluxo;
architecture fluxo of MUX2x1_fluxo is
begin
S<=(B AND C) OR (A AND NOT(C));
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity testbenchMUX2x1_fluxo is
end testbenchMUX2x1_fluxo;
architecture teste of testbenchMUX2x1_fluxo is
component MUX2x1_fluxo
port (A, B, C: in std_logic;
S: out std_logic);
end component;
signal sigA, sigB, sigC, sigS: std_logic;
begin
comp: MUX2x1_fluxo port map (sigA, SigB, sigC, sigS);
process
begin
sigA <= '0','1' after 2 ns,'0' after 4 ns;
sigB <= '1','0' after 3 ns,'1' after 5 ns;
sigC <= '0','1' after 3 ns,'0' after 6
ns;
wait;
end process;
end teste;
Processador.vhd
library ieee;
use ieee.std_logic_1164.all;
entity Processador is
port(dados_inout: inout std_logic_vector (15 downto 0);
endereco_out: out std_logic_vector (15 downto 0);
rd, wr: out std_logic);
end Processador;
architecture estrutura of Processador is
component alu_16bits is
port (EntA,EntB:in std_logic_vector (15 downto 0);
EntF: in std_logic_vector (1 downto 0);
saiS:out std_logic_vector (15 downto 0);
SaiN,SaiZ: out std_logic));
end component;
component controlador_cpu is
port (n,z,clk: in std_logic;
amux,mbr,mar,rd,wr,enc: out std_logic;
ula,sh:out std_logic_vector(1 downto 0);
a,b,c:out std_logic_vector(3 downto 0));
end component;
component decodicador4X16_estrutural is
port (EntDec: in std_logic_vector(3 downto 0);
enDec: in std_logic;
sDec: out std_logic_vector(15 downto 0));
end component;
component deslocador_estrutural is
port (EntA: in std_logic_vector(15 downto 0);
EntF: in std_logic_vector(1 downto 0);
SaiS: out std_logic_vector(15 downto 0));
end component;
component GSC is
port(T1,T2,T3,T4: out std_logic);
end component;
component incrementadorgen is
generic (tam: integer);
port (A: in std_logic_vector (tam - 1 downto 0);
resultado: out std_logic_vector(tam - 1 downto 0));
end component;
component latch is
port( D: in std_logic_vector(15 downto 0);
CK: in std_logic;
Q: out std_logic_vector(15 downto 0));
end component;
component logica_microsequenciamento_estrutural is
port(EntN,EntZ: in std_logic;
EntCond: in std_logic_vector(1 downto 0);
SaiS: out std_logic);
end component;
component memoria_controle is
port(Address: in unsigned (7 downto 0);
Dado: out std_logic_vector (31 downto 0));
end component;
component mux2x1_16 is
port (A,B:in std_logic_vector (15 downto 0);
C: in std_logic;
S:out std_logic_vector (15 downto 0));
end component;
component MBR is
port(barramento: inout std_logic_vector(15 downto 0);
toCPU: out std_logic_vector(15 downto 0);
fromCPU: in std_logic_vector(15 downto 0);
clock,rd,wr,controle : in bit);
end component;
component MAR is
port (Entrada : in std_logic_vector(15 downto 0);
CLK,Flag:in bit;
Saida: out std_logic_vector(15 downto 0));
end component;
component MIR is
port(RST,CLK:in bit;
D: in std_logic_vector(31 downto 0);
Q,NQ: out std_logic_vector(31 downto 0));
end component;
component ffD16 is
port(RST,CLK:in bit;
D: in std_logic_vector(15 downto 0);
Q,NQ: out std_logic_vector(15 downto 0));
end component;
component tristate is
port ( entrada: in std_logic_vector (15 downto 0);
oe: in std_logic;
saida: out std_logic_vector (15 downto 0));
end component ;
signal endereco, dados, csa, csb, csc, barramento_deslocador, entradaA, entradaB, barramentoA, barramentoB,
sai_desloc, saida_alu, entradaAluA, mbr_sai_interno: std_logic_vector (15 downto 0);
signal enderecoA, enderecoB, enderecoC: std_logic_vector (3 downto 0);
signal cabo_mux1, entrada_mc, saida_inc: std_logic_vector (7 downto 0);
signal saida_mc, sinais_controle: std_logic_vector (31 downto 0);
signal desvio_mux, habilita_decc, subclock1, subclock2, subclock3, subclock4, n, z: std_logic;
begin
GSC1:GSC port map (subclock1, subclock2, subclock3, subclock4);
decA:decodicador4X16_estrutural port map (enderecoA,1,csa);
decB:decodicador4X16_estrutural port map (enderecoB,1,csb);
EnableDec <= subclock4 and sinais_controle (20);
decC:decodicador4X16_estrutural port map (enderecoC,EnableDec,csc);
mux:mux2x1_16 port map(sinais_controle(7 downto 0),saida_inc, desvio_mux, cabo_mux1);
inc: incrementadorgen generic map (8) port map (entrada_mc, saida_inc);
MEMControle: memoria_controle port map (entrada_mc, saida_mc);
TIR: ffD16 port map (saida_mc, subclock1, sinais_controle);
lachA: laTch port map (entradaA, subclock1, barramentoA);
lachB: laTch port map (entradaB, subclock1, barramentoB);
amux: mux2x1_16 port map (mbr_sai_interno ,barramentoA, sinais_controle (31), entradaAluA);
ALU1: alu_16bits port map (entradaAluA, barramentoB, sinais_controle(28 downto 27), n, z, saida_alu);
desloc: deslocador_estrutural port map (saida_alu, sinais_controle(25), sinais_controle(26), sai_desloc);
LMS1: logica_microsequenciamento_estrutural port map (n, z, sinais_controle (30 downto 29), desvio_mux);
mar1: MAR port map (barramentoB, subclock3, sinais_controle(22), endereco);
mbr: MBR port map (sai_desloc, dados_in, sinais_controle (22), sinais_controle (21), sinais_controle (20),subclock4, mbr_sai_interno, dados);
regs: memoriat3 port map(sai_desloc, csa, csb, csc, subclock4, entradaA, entradaB);
rd <= sinais_controle (21);
wr <= sinais_controle (20);
end estrutura;
Registrador_Dados.vhd
library ieee ;
use ieee.std_logic_1164.all;
entity MBR is
port(barramento: inout std_logic_vector(15 downto 0);
toCPU: out std_logic_vector(15 downto 0);
fromCPU: in std_logic_vector(15 downto 0);
clock,rd,wr,controle : in bit);
end MBR;
architecture algoritmica of MBR is
begin
process(controle, clock, rd,wr)
begin
if (clock='1' and clock'event) then
if (controle = '1' ) then
if ( wr ='1') then
barramento <= fromCPU;
else
barramento<="ZZZZZZZZZZZZZZZZ";
end if;
elsif (rd = '1') then
toCPU <= barramento;
end if;
end if;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity teste_MBR is
end teste_MBR;
architecture testbench of teste_MBR is
component MBR is
port(barramento: inout std_logic_vector(15 downto 0);
toCPU: out std_logic_vector(15 downto 0);
fromCPU: in std_logic_vector(15 downto 0);
clock ,rd,wr,controle: in bit);
end component;
signal sigClk,sigRD,sigCTRL,sigWR: bit;
signal sigBarramento,sigtoCPU,sigfromCPU: std_logic_vector (15 downto 0);
begin
comp: MBR port map (sigBarramento,sigtoCPU,sigfromCPU,sigCLK,sigRD,sigWR,sigCTRL);
process
begin
sigClk <= not (sigClk) after 1 ns;
wait for 2 ns;
end process;
process
begin
sigCTRL <= '1','0' after 6 ns;
sigRD <= '0','1' after 5 ns,'0' after 10 ns;
sigWR <= '1','0' after 6 ns;
sigfromCPU <= "1010101010101010","1111111111111111" after 5 ns;
wait;
end process;
end testbench;
Registrador_Endereco.vhd
library ieee;
use ieee.std_logic_1164.all ;
entity MAR is
port (Entrada : in std_logic_vector(15 downto 0);
CLK,Flag:in bit;
Saida: out std_logic_vector(15 downto 0)
);
end MAR;
architecture algo_MAR of MAR is
begin
process (CLK,Flag)
begin
if (Flag = '1' and CLK = '1' and CLK'event) then
Saida <= Entrada;
end if;
end process;
end algo_MAR;
library ieee ;
use ieee.std_logic_1164.all ;
entity teste_mar is
end teste_mar;
architecture teste of teste_mar is
component MAR
port(Entrada : in std_logic_vector(15 downto 0);
CLK,Flag:in bit;
Saida: out std_logic_vector(15 downto 0)
);
end component;
signal sigIN, sigOUT: std_logic_vector(15 downto 0);
signal sigCLK, sigF: bit;
begin
comp: MAR port map (sigIN,sigCLK,sigF,sigOUT);
process
begin
sigCLK <= not(sigClk) after 1 ns;
wait for 2 ns;
end process;
process
begin
sigF <= '1', '0' after 3 ns, '1' after 5 ns ;
sigIN <= "1010001010001011","0001000100001101"
after 3 ns ,"0000001111010111" after 6 ns ;
wait;
end process;
end teste;
Registrador_microinstrucao.vhd
library ieee;
use ieee.std_logic_1164.all;
entity MIR is
port(RST,CLK:in bit;
D: in std_logic_vector(31 downto 0);
Q,NQ: out std_logic_vector(31 downto 0));
end MIR;
architecture estru_MIR of MIR is
component ffD
port(RST,CLK:in bit;
D: in std_logic;
Q,NQ: out std_logic);
end component;
begin
GEN:for I in 31 downto 0 generate
ff : ffD port map (RST, CLK, D(I), Q(I),NQ(I));
end generate ;
end estru_MIR;
library ieee;
use ieee.std_logic_1164.all;
entity teste_MIR is
end teste_MIR;
architecture teste of teste_MIR is
component MIR
port(RST,CLK:in bit;
D: in std_logic_vector(31 downto 0);
Q,NQ: out std_logic_vector(31 downto 0));
end component;
signal sigRST, sigCLK: bit;
signal sigD,sigQ,sigNQ :std_logic_vector(31 downto 0) ;
begin
comp:MIR port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
process
begin
sigCLK <='0', not (sigCLK) after 1 ns;
wait for 2 ns;
end process;
process
begin
sigD<="10111000101110011011100010111001","01000010000010000100001000001000" after 2 ns,"00000010000100010000001000010001" after 10 ns;
sigRST<='0', '1' after 4 ns;
wait ;
end process;
end teste;
RegistroLocal.vhd
library ieee;
use ieee.std_logic_1164.all;
entity ffD16 is
port(RST,CLK:in bit;
D: in std_logic_vector(15 downto 0);
Q,NQ: out std_logic_vector(15 downto 0));
end ffD16;
architecture estru_ffD16 of ffD16 is
component ffD
port(RST,CLK:in bit;
D: in std_logic;
Q,NQ: out std_logic);
end component;
begin
GEN:for I in 15 downto 0 generate
ff : ffD port map (RST, CLK, D(I), Q(I),NQ(I));
end generate ;
end estru_ffD16;
library ieee;
use ieee.std_logic_1164.all;
entity teste_ffD16 is
end teste_ffD16;
architecture teste of teste_ffD16 is
component ffD16
port(RST,CLK:in bit;
D: in std_logic_vector(15 downto 0);
Q,NQ: out std_logic_vector(15 downto 0));
end component;
signal sigRST, sigCLK: bit;
signal sigD,sigQ,sigNQ :std_logic_vector(15 downto 0) ;
begin
comp:ffD16 port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
process
begin
sigCLK <='0', not (sigCLK) after 3 ns;
wait for 5 ns;
end process;
process
begin
sigD<="1011100010111001","0100001000001000" after 2 ns,"0000001000010001" after 10 ns;
sigRST<='0', '1' after 4 ns;
wait ;
end process;
end teste;
Somador.vhd
library ieee;
use ieee.std_logic_1164.all;
entity somador is
port (A, B, vem1: in std_logic;
resultado, vai1: out std_logic);
end somador;
architecture fluxo of somador is
signal somando: std_logic_vector (8 downto 0);
begin
somando(0) <= a xor b;
somando(1) <= vem1 xor somando(0);
somando(2) <= a and b;
somando(3) <= vem1 and somando(0);
vai1 <= somando(2) or somando(3);
resultado <= somando(1);
end fluxo;
library ieee;
use ieee.std_logic_1164.all;
entity testbench_somador is
end testbench_somador;
architecture testbench of testbench_somador is
component somador is
port (A, B, vem1: in std_logic;
resultado, vai1: out std_logic);
end component;
signal sigA,sigB,sigVem1,sigResultado,sigVai1: std_logic;
begin
somador1: somador port map(sigA,sigB,sigVem1,sigResultado,sigVai1);
process
begin
sigA <= '0', '1' after 10 ns, '0' after 20 ns;
sigB <= '1', '0' after 5 ns, '0' after 20 ns;
sigVem1 <= '0', '1' after 10 ns, '0' after 15 ns;
wait;
end process;
end testbench;
SomadorGen.vhd
library ieee;
use ieee.std_logic_1164.all;
entity somadorGen is
generic (tam: integer);
port (A, B: in std_logic_vector (tam - 1 downto 0);
resultado: out std_logic_vector(tam - 1 downto 0));
end somadorGen;
architecture estrutura of somadorGen is
component somador is
port (A, B, vem1: in std_logic;
resultado, vai1: out std_logic);
end component;
signal result: std_logic_vector (tam - 1 downto 0);
signal vem1: std_logic_vector (tam downto 0);
begin
vem1(0)<='0';
som: for i in tam - 1 downto 0 generate
somn: somador port map (a(i),b(i),vem1(i),result(i),vem1(i+1));
end generate;
resultado <= result;
end estrutura;
library ieee;
use ieee.std_logic_1164.all;
entity testbench_somadorGen is
end testbench_somadorGen;
architecture testbench of testbench_somadorGen is
component somadorGen is
generic (tam: integer);
port (A, B: in std_logic_vector (tam - 1 downto 0);
resultado: out std_logic_vector(tam - 1 downto 0));
end component;
signal sigA, sigB, sigResultado: std_logic_vector (3 downto 0);
begin
somadorX: somadorGen generic map (4) port map (sigA, sigB, sigResultado);
process
begin
sigA<= "0000", "0001" after 5 ns, "0010" after 10 ns, "1111" after 20 ns;
sigB<= "0000", "0001" after 5 ns, "0001" after 10 ns, "1001" after 15 ns, "1111" after 20 ns, "0001" after 25 ns;
wait;
end process;
end testbench;
Tristate.vhd
library ieee;
use ieee.std_logic_1164.all;
-- Tristate 16 bits
entity tristate is
port ( entrada: in std_logic_vector (15 downto 0);
oe: in std_logic;
saida: out std_logic_vector (15 downto 0));
end tristate ;
architecture estrutura of tristate is
signal entrada_tri, saida_tri: std_logic_vector (15 downto 0);
begin
saida <= entrada when oe = '1' else "ZZZZZZZZZZZZZZZZ";
end estrutura;
library ieee;
use ieee.std_logic_1164.all;
entity testbench_tristate is
end testbench_tristate;
architecture teste of testbench_tristate is
component tristate is
port ( entrada: in std_logic_vector (15 downto 0);
oe: in std_logic;
saida: out std_logic_vector (15 downto 0));
end component;
signal ent, sai: std_logic_vector (15 downto 0);
signal sinal:std_logic;
begin
a1: tristate port map (ent,sinal,sai);
process
begin
ent <="1010101010101010", "1111111111111111" after 12 ns;
sinal <= '0', '1' after 5 ns, '0' after 13 ns, '1' after 20 ns;
wait;
end process;
end teste;Mais conteúdos dessa disciplina
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